5.FPGA FOR BEGINNERS- SR Latch in VHDL on the Basys3 Board

Introduction

In this tutorial, we will learn how to create an SR Latch using VHDL on the Basys 3 FPGA board with the Vivado software. This project is a great way to understand basic digital logic design and FPGA programming. Additionally, we will address and resolve the DRC LUTLP-1 error that may occur during the implementation.

Step 1: Setting Up Your Environment

• Install Vivado: Ensure you have the latest version of Xilinx Vivado installed on your computer. This software is essential for programming the Basys 3 FPGA board.
• Connect the Basys 3 Board: Use a USB cable to connect your Basys 3 board to your computer. Ensure that the board is powered on.

Step 2: Create a New Project in Vivado

• Open Vivado: Launch the Vivado software.
• Start a New Project:
  • Click on "Create New Project."
  • Follow the wizard to give your project a name and select the appropriate location.
• Select the FPGA Device:
  • Choose the Basys 3 board from the device list. This will automatically set the correct parameters for your project.

Step 3: Write the VHDL Code for the SR Latch

• Create a New VHDL Module:
  • Right-click on "Design Sources" and select "Add Sources."
  • Choose "Create File" and name it SR_Latch.vhdl.
• Code the SR Latch:
  • Open the SR_Latch.vhdl file and input the following code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_Latch is
    Port ( S : in STD_LOGIC;
           R : in STD_LOGIC;
           Q : out STD_LOGIC;
           Qn : out STD_LOGIC);
end SR_Latch;

architecture Behavioral of SR_Latch is
begin
    process(S, R)
    begin
        if (S = '1' and R = '0') then
            Q <= '1';
            Qn <= '0';
        elsif (S = '0' and R = '1') then
            Q <= '0';
            Qn <= '1';
        elsif (S = '0' and R = '0') then
            Q <= Q; -- Hold state
            Qn <= Qn; -- Hold state
        else
            Q <= 'Z'; -- Invalid condition
            Qn <= 'Z'; -- Invalid condition
        end if;
    end process;
end Behavioral;

Step 4: Resolve DRC LUTLP-1 Error

• Understanding the Error: The DRC LUTLP-1 error indicates that your design has unconnected inputs or outputs.
• Check Connections:
  • Ensure all ports in your VHDL code are connected properly in the Vivado schematic.
• Update Constraints:
  • Open the constraints file for your project (typically named *.xdc).
  • Make sure to assign the physical pins on the Basys 3 board to the inputs (S and R) and outputs (Q and Qn) of your SR Latch.

Step 5: Simulate Your Design

• Create a Testbench:
  • Add a new VHDL file for a testbench to simulate the SR latch behavior.
• Run the Simulation:
  • Use Vivado's simulation tools to test your SR Latch with various input combinations for S and R, verifying the output Q and Qn.

Step 6: Implement and Program the FPGA

• Synthesize the Design: Click on "Synthesize" to compile your design.
• Implement the Design: After synthesis, perform the implementation step.
• Generate Bitstream: Once implemented, generate the bitstream file.
• Program the FPGA:
  • Click on "Open Hardware Manager."
  • Connect to your Basys 3 board and program it with the generated bitstream.

Conclusion

In this tutorial, we successfully created an SR Latch in VHDL on the Basys 3 FPGA board, resolved the DRC LUTLP-1 error, and programmed the FPGA. By following these steps, you should now have a basic understanding of VHDL design and FPGA programming. For further exploration, consider experimenting with different types of latches or flip-flops, or dive deeper into other digital design concepts.